1. Field
This disclosure relates generally to memories, and more specifically, to a method for making a stressed non-volatile memory device.
2. Related Art
Semiconductor non-volatile memories (NVMs), and particularly flash electrically erasable, programmable read-only memories (EEPROMs), are widely used in a range of electronic equipment from computers, to telecommunications hardware, to consumer appliances. The flash EEPROM is encountered in numerous configurations. In particular, a floating-gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, “floating”).
In another configuration, a charge storage layer comprising nanocrystals as the charge storage mechanism is used in place of the floating gate. The nanocrystals function as isolated charge storage elements.
As devices continue to become smaller with advances in semiconductor device technology, the performance of the individual memory cells has become more important. The read function in particular suffers with reduced device performance.
In many prior art non-volatile memory (NVM) devices, the charge storage layer is separated from the channel region by a relatively thin tunnel dielectric layer. There can be a problem of charge leakage from the charge storage layer to the underlying channel. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, the thickness of the tunnel dielectric is often increased. However, a thicker tunnel dielectric requires higher programming and erasing voltages for storing and removing charge from the charge storage layer as the charge carriers must pass through the thicker tunnel dielectric. In many cases, higher programming voltages increase power consumption and may require the implementation of charge pumps in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
Therefore, what is needed is a NVM cell with improved performance.